For a transformer-coupled (stub-coupled) RT, MIL-STD-1553B recommends (but does not require) a maximum stub length of 20 feet connecting between a bus coupling box and a single terminal (BC, RT, or monitor). The main intent of this stipulation is to minimize the stub loading on the main bus. Excessively long stubs and/or stubs terminated in low impedances can load down the main bus and result in transmission line reflections, and therefore waveform distortions. This can have the effect of increasing the bit error rate for terminals receiving data on the bus or, in extreme circumstances, cause terminals to stop receiving completely.

However, it is not all that uncommon for implementations to exceed the 25 foot recommendation. If you don't have too many of these types of loads on a particular 1553 bus (and the bus is not too long), then the terminals on it should operate reliably.

A transformer-coupled BC or RT is required to transmit a stub voltage of 18 to 27 volts peak-to-peak on its stub, which translates to a voltage on the main bus in the range of 6.36 to 9.54 volts peak-to-peak. A direct-coupled BC or RT is required to transmit 6.0 to 9.0 volts on the bus. Using the lower (direct-coupled) number and assuming a very short data bus (i.e., no attenuation on the main bus) this results in a minimum received voltage of 4.24 volts peak-to-peak on the stub for a transformer-coupled BC or RT. 

In considering cable attenuation, MILSTD-1553B requires that a bus network must be designed to provide a voltage between 1.0 and 14.0 volts peak-to-peak at the input to every stub-coupled terminal. The minimum stub signal of 1.0 volt corresponds to a voltage of 1.41 volts peak-to-peak on the main bus. Assuming a minimum voltage transmitter, this allows for an attenuation ratio for the main bus of 4.24 to 1 (6/1.41), or 12.6 dB. This provides for a wide margin, in terms of cable lengths as well as terminal transmitter output and receiver threshold characteristics.

MIL-STD-1553B also requires that a transformer-coupled receiver must accept (in the case of an RT, must respond to) any voltage in the range of 0.86 to 14.0 volts peak-to-peak. This provides 0.14 volts margin between the lowest terminal input voltage and the maximum receiver threshold voltage. In addition, a BC or RT is required to not accept a voltage below 0.2 volts peak-to-peak (i.e., an RT receiving a voltage below this level must not respond).

Of course, the other consideration is transmission line reflections. Reflection problems can interfere with the operation of terminals on the bus. However, assuming there is a limited number of long stubs (longer than 20 feet), the bus should operate reliably.

For the effect of the 25 foot stub cable, refer to Figure I-1.7 on page I-16 in our MIL-STD-1553 Designer's Guide, Sixth edition. For a transformer-coupled terminal, assuming a "1553B transformer", increasing the stub length from 20 to 25 feet will have the effect of reducing the (worst-case) impedance looking from the bus from about 500 ohms to 400 ohms, representing a 25% increase in the stub loading. Note that a "1553B transformer" implies a bus coupling transformer with a minimum open circuit impedance of 3000 ohms, as specified in paragraph 4.5.1.5.1.1.1 of MIL-STD1553B.

A. MIL-STD-1553B has no maximum bus length, and I have heard of instances where 1000 foot buses have operated successfully. You need to consider the following:

1. You may want to perform a bus loading analysis/simulation. That is, consider the cable attenuation (for a long bus, you can buy heavier twinax cable with lower resistance per foot, and therefore lower attenuation), the number of bus taps (stubs), and the length and spacing of the stubs. I suggest that you either simulate this or build a mock-up. However, for a 300 foot bus with a reasonable number of terminals, it is unlikely that you will see a problem.
2. You need to consider the BC response timeout time value. A 1000 foot bus results in a roundtrip time of 3 to 4 µs. With our ACE,

Mini-ACE, and Enhanced MiniACE series bus controllers, the minimum nominal BC timeout value is 18.5 µs. In addition, you may program this parameter for higher nominal timeout values of  22.5, 50.5, or 128.0 µs.

For the impedance measurement, we (DDC) use an HP 4192 impedance analyzer. The correct voltage for measuring input impedance, per the 1553 test plan, is in the range from 1.0 to 2.0 Vrms, applied on the stub. Assuming a 15 volt transceiver and therefore a stub-coupled turns ratio of 2:1, this results in a voltage of 2.0 to 4.0 Vrms applied at receiver inputs to the 1553 terminal hybrid. In order to get a stable impedance measurement, the guard conductor from the analyzer needs to be connected to the transformer center tap on the stub side.

At one time, the noise gate was required for our older generation series terminals, the BUS-61553 (AIM-HY) and the BUS-61559 (AIM-HY'er).

However, the need for the noise gate has been eliminated by the decoder design used in the ACE, Mini-ACE (Plus), the Enhanced Mini-ACE, and the SP'ACE. The new decoder provides improved filtering at the end of a received message, eliminating the need for the noise gate.

There are several additional requirements:

1. The stub-coupled transmitter voltage must be a minimum of 20 volts peak-to-peak (the requirement for MIL-STD-1553B is 18 volts peakto-peak).
2. There are requirements regarding the RT address. Part of these may be satisfied by latching the RT address (from the 1760 connector) soon after power turn-on. For more details, refer to the answer to the next question.
3. A 1760 compliant RT must be able to respond on the bus within 150 ms following power turn-on. At this time, it is permitted to respond with the "Busy" status word set. This indicates that while the RT is "alive," it is not yet able to transfer data. Alternatively, it may respond with valid data.
4. Within 500 ms following power turn-on, the RT must be responding with data as defined by the 1760 standard, with the "Busy" status bit not set. This means that the RT's host processor must be fully up and running at this time.
5. For a bus controller, most of the MIL-STD-1760 requirements are fulfilled by means of software, rather than by hardware. One "gray area" is with regards to the 1760 requirement to transmit and verify (at the receiving end) a checksum with every message.

The checksum requirement may be implemented by either hardware or software. DDC's opinion is that it is better to fulfill this requirement in software rather than hardware. The reason for this is that a software verification provides for a complete "end-to-end" integrity verification.

What we mean by "end-to-end" is that the checksum, if implemented in software, encompasses the operation not only of the 1553 (1760) communications interface, but also of the BC's and RT's host microprocessors and memory, along with the BC's and RT's embedded processor and firmware.

Keep in mind that the integrity of the 1553 (1760) communication link is still checked by the BC and RT hardware, by means of the parity bit transmitted and checked with each word of every message transmitted across the bus.

Yes. There are several considerations:

1. For MIL-STD-1760, the RT address must be provided from the 1760 connector. That is, it must not be programmed by the RT's host processor software.
2. When any of the RT address signals are connected to logic "0,"

there must be a minimum of 5 mA of current in the wire to the 1760 connector. Assuming a 5V power supply, this implies the need for pull-up resistors of less than 1K between +5V and each of the RT address signals.

3. Note that for routing the RTAD signals to the 1760 connector, it is suggested that some form of ESD protection - either capacitors or clamping diodes - be used. Note that this is just a suggestion, it is not a MIL-STD-1760 requirement.
4. The RT address must be latched into the RT within 10 ms following power turn-on. In addition, it must not change after it has been latched. There are a few different methods for doing this, depending on one's interpretation of the 1760 standard: 

With Mini-ACE, there are several possible means for specifying an RT address for MIL-STD-1760 applications. A common element of all of these methods is that the RT address input signals must be connected to the 1760 connector. The possible methods are as follows:

1. Use the RT address inputs directly by connecting RT_AD_LAT to logic "0."
2. Connect the RT address signals to the 1760 connector, connect RT_AD_LAT to logic "1," and have the host processor latch the data from the Mini-ACE RT address inputs under software control, by means of Configuration Registers 3, 4, and 5.
3. Use a reset circuit to provide a rising edge to RT_AD_LAT sometime after power turn-on reset (that is, after the MSTCLR input to the MiniACE has settled to logic "1"). This edge will cause the signals on RTAD4-RTAD0 and RTADP to be internally latched. By doing this, if one of the wires to the 1760 connector breaks following turn-on (e.g., when the 1760 connector disengages when the store is fired), the RT address will remain latched internally.

 RT Auto-Boot with the Busy bit set is a feature for the BU-65179 RT version of the Mini-ACE and the versions of the Enhanced Mini-ACE with 4K X 16 RAM, but not of the BU-65178 and BU-61588 Mini-ACE, and the BU-61688/89 Mini-ACE Plus. The BU-65179's "AUTO_BOOT" feature (i.e., to initialize to RT mode with the Busy bit set at power turn-on) is intended for MIL-STD-1760 applications. This helps the 1760 RT designer meet the requirement to be responding to 1553 commands within 150 ms after power-up. By comparison, the BU-65178 RT initializes to "Idle" mode, rather than RT mode, at power turn-on. In "Idle" mode, the host processor must write to Configuration Register #1 to initialize the BU-65178 to RT mode. 

Yes. The ACE, Mini-ACE, and Enhanced Mini-ACE are compliant to STANAG-3838. In addition, these terminals include functionality to accommodate the requirements for EFA, the EuroFighter Aircraft. These features include:

1. Providing a mechanism for separating received broadcast data from non-broadcast data. This requirement is met by providing an option for two separate lookup tables; this is, the use of either a single received/broadcast table, or separate receive and broadcast lookup tables.
2. Provide an option to automatically clear the Service request status word bit following reception of a Transmit vector word mode command.
3. Provide options to automatically clear the value of the internal time tag to zero following reception of a Synchronize without data mode command, and/or to automatically load the time tag register with the received data word following reception of a Synchronize with data mode command. In addition, the Enhanced Mini-ACE bus controller includes an option to automatically transmit the contents of the time tag register as the data word for a Synchronize (with data) mode command.
4. The TX_INH_A and TX_INH_B inputs are pinned out of the MiniACE (Plus) hybrids. This is a requirement for STANAG-3910 for EFA.
5. An RT requirement to provide a means of ensuring data consistency. The Mini-ACE (and Enhanced Mini-ACE) RT's circular buffering and double buffering mechanisms are provided specifically for this purpose.
6. In its default RT configuration, the Mini-ACE treats subaddress 31, as well as subaddress 0, as mode code subaddresses, and provides the capability to illegalize individual mode code commands for either or both of these subaddresses.
7. There is capability for the host processor to read the value of the RT flag status bit (via bit 7 of Configuration Register #1 in RT ENHANCED MODE).
8. EFA/STANAG-3838 compliant RTs must not implement the DYNAMIC BUS CONTROL, SELECTED TRANSMITTER SHUTDOWN, and OVERRIDE SELECTED TRANSMITTER SHUTDOWN mode commands. The Mini-ACE provides the capability to illegalize any or all of these mode codes, under software control.
9. STANAG-3838 for EFA requires that all RTs must implement the following mode commands: Synchronize without data, Synchronize with data, Transmit status word, Initiate self-test, Override transmitter shutdown, Reset remote terminal, Transmit vector word, Transmit last command, and Transmit BIT word. The ACE, Mini-ACE (Plus), and Enhanced Mini-ACE RTs implement all of these.
10. In addition to Service request, STANAG-3838 for EFA requires implementation of the following RT status word bits: Broadcast command received, Busy (per MILSTD-1553B Notice 2), Subsystem flag, and Terminal flag. It requires that the Dynamic bus control acceptance bit not be used. All of the ACE series RTs meet all of these requirements.
11. All ACE RTs meet the EFA STANAG-3838 RT requirement for implementing all 30 non-mode code subaddresses (1-30).
12. Regarding RT address: EFA/STANAG-3838 requires that this be user settable in accordance with MIL-STD-1553B Notice 2. Notice 2 requires that "no single point failure shall cause a terminal to validate a false address." The ACE series RTs meet this requirement by the inclusion of its RTADP (RT Address Parity) input signal.

Our MIL-STD-1553 terminals are used in a wide variety of avionics applications. These include mission computers, flight control computers, displays, transducers, data storage systems, memory loader/verifiers, stores management systems, and missiles. Our 1553 terminals are also used in space applications, including satellites, launch vehicles, space vehicles, and the International Space Station. MIL-STD-1553 is also used on tanks and other ground vehicles.

(1) The ACE includes a TAG_CLK Input signal. There is no TAG_CLK input on the standard Mini-ACE. We have found that most ACE users do not require this input signal. Without using TAG_CLK, you have software programmable options of 2, 4, 8, 16, 32, and 64 µs/LSB, with 64 µs/ LSB being the most commonly used time tag resolution. Use of the TAG_CLK input (for the original ACE) allows for other resolutions; for example, 10 or 20 µs/LSB.

2. The Mini-ACE does not include a MEMENA-OUT output signal. This feature is not required for the MiniACE buffered mode. If you design for transparent mode, the signal  MEMENA-OUT (low) may be derived by gating IOEN (low) OR DTACK (low).
3. The Mini-ACE (Plus) does not  bring out the INCMD output signal.
4. For Mini-ACE (Plus), the register bit EXPANDED CROSSING ENABLED (bit 11 of Configuration Register #6) is obsolete. That is, expanded zero crossing, in which the 1553 Manchester decoders sample using both edges of the clock input (CLK_IN) is always enabled. As a result, the MiniACE's duty cycle tolerance for CLK_IN is tightened from 33% to 67%, to 40% to 60%.

 Yes.

1. For Mini-ACE, the TX_INH_A and TX_INH_B input signals are pinned out. For the ACE, these signals are generally not brought out, except for the BU-61586X6 (5 volt) versions.
2. The BU-61688 (Mini-ACE Plus) has 64K X 16 of internal shared RAM, in comparison to the BU-61586 (ACE), which has 12K X 16 RAM.
3. The BU-61688 Mini-ACE, like the BU-61586 ACE, allows the use of 16 MHz or 12 MHz clock inputs. However, if your board has a 10 MHz or 20 MHz clock available, the BU-61689 version of the Mini-ACE Plus can use either of these.
4. In the BU-61688's (Mini-ACE Plus) BC mode, register #0B, the BC FRAME TIME REMAINING REGISTER, will return the actual frame time remaining. For the BU-61586 ACE, this register will return a value of zero.

1. They are not pin compatible. The BU-61585 is in a 1.0 X 1.9 inch package. The BU-61689 is in a 1.0 X 1.0 inch package.
2. The BU-61585 runs off either a 12 MHZ or 16 MHZ clock, while the BU-61689 runs off a 10 MHZ or 20 MHZ clock. The BU-61688 is identical to the BU-61689, but runs off a 12 MHZ or 16 MHZ clock.
3. BU-61585 has 12K X 16 of RAM (or, alternatively, can be configured to have 8K X 17), while the BU-61689 (or BU-61688) has 64K X 16 of RAM

Yes. The Mini-ACE hybrid, which incorporates a 5V (only) transceiver (there are no 15V or 12V versions of the MiniACE) has passed the MIL-STD-1553 RT Validation Test Plan (VTP). This test comprehensively exercises both the transceiver and protocol (logic) portions of the Mini-ACE hybrids. The Mini-ACE passed the RT VTP at all three temperatures (-55, +25, and +125 degrees C). We have a test report available. If you would like a copy, we can supply it. In addition, Appendix E of our ACE User's Guide is a report of the BU-61580D2-110 ACE passing the RT VTP. The RT protocol chip used in the Mini-ACE and Mini-ACE plus (BU61688/89) hybrids includes the same RT protocol functionality as the protocol chip used in the original BU-61580 ACE hybrid.

For the Mini-ACE (BU-65178/61588), the upper four address lines (A15-A12) are not used. However, use of  the 4K RAM (Mini-ACE) version with the 4 address lines connected to A15-A12 provides a compatibility path to the BU-61688/89 Mini-ACE Plus with its 64K of RAM. For the BU-65179 MiniACE RT with auto-boot, these signals take on different functions, and should not be connected to A15-A12.

These provide a hardware mechanism for shutting down a faulty 1553 transmitter. In addition, these signals may be used to ensure that a Mini-ACE (Plus) cannot transmit when configured for monitor mode. Also, the TX_ INH inputs provide compliance to the EFA/STANAG-3910 spec.

For normal operation (i.e., assuming that you want to use, rather than shut off, the 1553 transmitters), the TX_ INH_A and TX_INH_B inputs should be hardwired to logic "0" (ground). Make a direct connection to ground, rather than through a pull-down resistor. A pull-down resistor (e.g., 10K ohms) will not provide a reliable logic "0" connection, due to leakage current (the max leakage I_IL is about 400 µA).

Sort of. The memory configuration of the ACE/Mini-ACE's buffered mode is referred to as "shared RAM", rather than DMA. However, in operation, the shared RAM interface uses a DMAtype mechanism in that there are data transfers between the Mini-ACE's protocol logic (encoder/decoder and memory management logic) and the internal shared RAM, that take place not under CPU control.

That is, these transfers take place autonomously, independent of the host CPU. Since the host processor may also access this internal shared RAM, the Mini-ACE includes internal arbitration logic. This logic acts as a "traffic cop," to enable, at any point in time, for either the host processor or the Mini-ACE's internal logic, but not both simultaneously, access to the shared RAM.

In 1995, we had radiation testing performed on a BU-61581 ACE, with 1.25 micron J' protocol chip and 15V transceiver. Quoting from the report of this testing: at 2.8K rads, 5K rads, and 10K rads; and, for neutron fluences of 1.20•10¹² and 2.80•10¹², "The devices encountered no failures at this level." There were no single event effects exhibited at proton fluences of 1.0•10¹⁰ protons/cm².

As long as you're not using bus B, there's no need for a coupling transformer or termination resistors.

A. In the original ACE, the analog (transceiver) and digital grounds are not connected together inside the hybrid. In the Mini-ACE, as a means of reducing the effects of ground bounce, these grounds are connected together inside the hybrid. Basically however, the same rules apply: when transmitting, the large ground currents flow through the transformer (primary) center tap, not through the hybrid ground pins. Therefore, you still need to:

1. Connect all three Mini-ACE ground pins directly to the (digital) ground plane.
2. Use heavy ground traces to the transformer center tap connections.
3. This trace (to the transformer center taps) should connect through a low-impedance path to the +5V power supply return. Alternatively, you can connect this trace directly to the board's ground plane, assuming that the ground plane serves as both analog and digital ground (and return paths).
4. Of course, the ground and supply planes should NOT extend directly under the transformers or the analog signal traces. The added capacitance could make the terminal's input impedance fall below the 1553B stub-coupled minimum of 1000 ohms.

For the BU-61588, it is recommended to put individual 10 µf and 0.1 µf capacitors near each of the two transceiver power pins (20 and 72). Pin 72 is the +5V power input to the Channel A transceiver, while pin 20 is the +5V power input to the Channel B transceiver. To minimize the trace lengths (and therefore parasitic inductance) to each of these power inputs, it is best to provide separate decoupling for each.

For the BU-65179, CLK_SEL_1 and CLK_SEL_0 are used to designate the frequency of the CLK_IN input as follows:

As for the RT_BOOT_L signal: if it is connected to logic "1", the BU-65179 initializes in "Idle" mode. In this case, it is necessary for the host processor to write values of logic "1" and logic "0" to bits 15 and 14 respectively of Configuration Register #1 to put the BU-65179 online as a functioning (responding) RT. In addition, all of the RT status word bits will be either set or cleared as the result of writing to Configuration Register #1.

If RT_BOOT_L is connected to logic "0," the BU-65179 will initialize as a functioning RT without having to write to onfiguration Register #1. In addition, the RT status word "Busy" bit will initialize as set, while all of the other RT status word bits will initialize as cleared. That is, the BU-65179 RT will respond with its "Busy" bit set immediately following power turn-on.

For Mini-ACE (Plus) and Enhanced Mini-ACE, the BC provides a "time-tonext-message" parameter (rather than true "intermessage gap time") for each BC message. The "time-to-next-message" parameter defines the time from the start of the current message to the time of the start of the subsequent message.

In addition, the BC architecture of the Enhanced Mini-ACE enables you to implement a true "intermessage gap time" function by means of the DLY (delay) instruction. The delay time is programmable in 1 µs steps, up to 65.535 ms. The overall intermessage gap time will then be approximately 10 µs plus the value of the DLY parameter.

The BC END_OF_FRAME interrupt is issued at the completion of the last message of the frame, regardless of whether or not the Intermessage Gap Time (time-to-next-message) timer and/or the BC frame timer have timed out.

The Time Tag word is written to the BC descriptor stack during the start-ofmessage sequence and again during the end-of-message sequence.

For BC operation, it doesn't matter. However, if you plan on running the ACE/Mini-ACE self-test vectors, you must connect the RT address inputs RTAD4-RTAD0 to a valid RT address (0 to 30) with correct parity (i.e., odd parity for RTADP) in order for the selftest vectors to pass

The Mini-ACE's RT address signals include internal pull-ups. Actually, these are active current sources (from +5V), with the current values between approximately 50 and 400 µA. For best noise immunity, the RT address inputs should be connected directly to either +5V or LOGIC GROUND. In particular, pull-down resistors should not be used.

No. The size of the BC/RT command stack is programmable by means of bits 14 and 13 of Configuration Register #3. The four choices are:

For example, if bits 14 and 13 are both "0," the stack will roll over every 256 words, or 64 messages. The stack will roll over at an address equal to modulo the programmed stack size (e.g., 256, 512, ...).

No, the ACE does not include an explicit BC-MT mode. However, with the Mini-ACE bus controller mode, you essentially get a monitor for "free." In the ACE's BC message block, all of the words of a message are stored: that is, the BC's Command Word, the RT's Status Word (including both status words for an RT-to-RT transfer), and any and all Data Words transmitted by the BC or the RT. In addition, the Mini-ACE will flag any error condi-

tions: either failure of its own loopback test, and/or any no responses or errors in responses from RTs. So, in essence, you're getting all the functions of a bus monitor with the ACE's BC mode. Also, the Mini-ACE does include a combined RT/Monitor mode. In this mode, the ACE operates as a full-function RT for one RT address, and a selective message monitor for all other RT addresses.

For synchronizing between two MiniACEs, the external trigger is probably a good mechanism to use. To use the external trigger feature, you need to program bits 8, 7, and 6 of Configuration Register #1 as follows:

Bit 8 (FRAME AUTO-REPEAT):

logic "1"

Bit 7 (EXTERNAL TRIGGER ENABLED):

 logic "1"

Bit 6 (INTERNAL TRIGGER ENABLED):

logic "0"

This will configure the Mini-ACE for a "single frame," such that each frame may be initiated by a rising edge to the EXT_TRIG input signal, or by a software start command. The EXT_TRIG input signals should be connected together to a circuit generating this rising edge. By so doing, the Synchronize mode commands from the two Mini-ACEs will be very tightly synchronized.

Alternatively, you could use the software start mechanism; i.e., writing a value of 02h to the Start/Reset Register to each of the two Mini-ACEs. As long as you perform these two write cycles within a few microseconds, the start of transmission for the two Synchronize (without data) mode commands will be tightly synchronized.

There are three methods:

1. Hardwire RT_AD_LAT to logic "0." This will configure the RT address to be hardwired, by means of RTAD4-RTAD0 and RTADP.
2. Hardwire RT_AD_LAT to logic "1." In this configuration, the BU-65178's RT address will be programmable by means of Configuration Register #5. Note that when you write Configuration Register #5, the RT address will be latched from the RTAD4-RTAD0 and RTADP pins, and not from the processor address bus (D15-D0). However, if you connect RTAD4 to D5 .... RTAD0 to D1, and RTADP to D0, this will allow the RT address to be software programmable.

3. Include a circuit to provide a low-tohigh transition on the RT_AD_LAT input pin (sometime after MSTCLR has settled to logic "1"). This will cause the values presented on RTAD-4-RTAD0 and RTADP to be latched internally on this rising edge.

For the BU-65178 RT Mini-ACE, the only function of the SSFLAG/EXT_ TRIG input signal is as a SSFLAG

(Subsystem Flag) input. The "EXT_TRIG" function is not applicable to the BU-65178 RT. EXT_TRIG is a BC and Monitor function that is only applicable to the BU-61588 Mini-ACE BC/RT/MT, and the BU-61688/89 Mini-ACE Plus BC/RT/MT.

If SSFLAG is connected to logic "0," this will cause the Subsystem Flag bit in the RT Status word to be set to logic

"1." If SSFLAG is connected to logic "1," the value of Subsystem Flag will be determined by the software programming of Configuration Register #1. Therefore, if you don't intend to use this function, I recommend that you hard-

wire SSFLAG/EXT_TRIG to logic "1."

One use of the SSFLAG input is to provide a hardware mechanism for a processor watchdog timer to be able to signal to the 1553 RT that it has timed out (i.e., that the processor has hung up).

Yes. There is a way of causing the RT Status Register to update. It involves use of the Enhanced Mini-ACE's test

mode. Here's what you need to do:

1. Cause the watchdog timer to timeout, which will cause the Enhanced Mini-ACE's SSFLAG input signal to be logic "0."
2. Read the RT Status Word Register (register address 0E). If SUBSYSTEM FLAG, bit 2 of this register, returns logic "1," then you can skip the following steps. If this bit is logic "0," then you need to perform steps (3) through (7).

3. Make sure that the Enhanced MiniACE is programmed for RT mode, and that ENHANCED MODE is enabled; i.e., bit 15 of Configuration Register 3 is logic "1."
4. Read, and  then re-write, Configuration Register #4, setting the value of the three lower bits to 111 (binary). This will put the Enhanced Mini-ACE in GENERAL TEST MODE.

5. Write a value of 2000 (hex) to Test Mode Register 3 (register address 13 (hex)). This will cause the RT Status Word Register to update (as if a message has been received from the BC).

6. Read,  and  thenre-write, Configuration Register #4, this time setting the value of the three lower bits to 000 (binary). This will put the Enhanced Mini-ACE back into its normal RT mode of operation.

7. Once again, read the RT Status Word Register (register address 0E). If SUBSYSTEM FLAG, bit 2 of this register, returns a value of logic "1," then the test has passed.

The Mini-ACE's software programmable RT address does not require an external register. For the BU-65178/79 or BU-61588 Mini-ACE or the BU-61688/689 Mini-ACE Plus, the steps to use the software programmable RT address feature are as follows (the first two steps are hardware design; the last four steps are software programming):

1. Connect the signal RT_AD_LAT to logic "1."
2. Connect RTAD4 to data bus D5, RTAD3 to D4, …, RTAD0 to D1, and RTADP to D0.
3. Program the ACE for ENHANCED MODE, by setting bit 15 of Configuration Register #3 to logic "1."
4. Enable the RT address to be software programmed by setting LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5 (bit 3 of Configuration Register #4) to logic "1."
5. Program the RT address by writing to Configuration Register #5, using the bit mapping defined in step (2).
6. To prevent the software from inadvertently changing the RT address, clear LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5 (bit 3 of Configuration Register #4) to logic "0."

Yes. If the host sets SERVICE REQUEST to logic "0" between the SOM and EOM sequences for a Transmit vector word mode code message, the ACE RT will respond with the Service Request status bit equal to "0," and the SERVICE REQUEST register bit will automatically clear to logic "1." Therefore, the BC will never see the Service request bit set to logic "1." The rationale for this is that the BC should only send a Transmit vector word mode command after it has detected a Service request bit of logic "1" in a previous message.

The Time Tag counter is loaded immediately (i.e., asynchronously) following receipt of the data word for a Synchronize (with data) mode code. In addition, the 64 µs clock circuit is reset to zero at this time. That is, the time tag counter won't increment an LSB until a full 64 µs has elapsed.

For a receive mode command with data, the data word will be stored in both places: the third word of the message descriptor and the enhanced mode code data table. For mode commands without data, the third word of the descriptor will not be written to. For a transmit mode code command, the data will be read from the enhanced mode code data table and written to the third word of the descriptor.

The way the subaddress double buffering works is that after a valid message is received to a receive(/broadcast) or broadcast subaddress with double buffering enabled, then bit 5 of the lookup table pointer will be toggled.That is, the updated lookup table pointer value = (old lookup table pointer value XOR 32), and not (old lookup table pointer + 32).In other words, if the pointer's value is initially XXXX XXXX XX00 0000, it becomes XXXX XXXX XX10 0000. Similarly, if it's value is XXXX XXXX XX10 0000, it "ping-pongs" to a value of XXXX XXXX XX00 0000.

A BU-61580 RT configured with an incorrect RT Address parity bit will not receive or respond to commands to its own RT address. Note however that the BU-61580 will still be able to receive commands and data sent to the broadcast address (address 31).

Yes. That way, you can "ping-pong" between the two areas. While one is storing 1553 monitored data, the second one can be read out by the host processor.

Yes, the command and/or data stack pointer(s) will roll over to the top of the stack. As you point out, this can cause message corruption. What I suggest to avoid such a problem is that when your host processor initializes the stack pointer, to position it down from the top.

In the case of the monitor data stack, I would allow for 35 words at the top of the stack, to accommodate the maximum size message to be received; i.e., an RT-to-RT transfer, with the second command word + 32 data words + 2 status words. Similarly, for the monitor command stack, I would suggest initializing the stack pointer such that there are four locations -- the size of one message descriptor -- free at the top of the stack.

For the BU-61588 (4K internal RAM), what I would suggest is to use a monitor command stack size of 256 words for each of area A and area B. Likewise, for the monitor data stack, I would use a stack size of 1024 words for each of the two data stacks.

For the case of the Enhanced MiniACE, the 50% rollover interrupt feature should be used. That is, the monitor may be programmed to issue interrupt requests when the monitor data stack and/or the monitor command (descriptor) stack is 50% or 100% full. In this way, the host can read data from the most recently filled half data stack or half descriptor stack, while the monitor continues to store new data received from the 1553 bus in the other half stack.

For the command stack, the command stack rollover interrupt occurs at the beginning of a received message. For the monitor data stack rollover, the interrupt occurs at the end of the message that resulted in the rollover. In either case, the event will be reflected in the Interrupt Status Register (assuming that interrupts are enabled for these events).

If you initialize for a Command Stack size of 256, and initialize the Command Stack Pointer A (location 0x0102) to a value of 0x0600, it will increment by four (4) at the start of each received (monitored) message. That is, it will increment to 0x0604, 0x0608, .... 0x06F8, 0x06FC, before rolling back to 0x0600.

By so doing, note that the 4-word descriptor for the first monitored message received and stored will be stored in locations 0x0600-0x0603. The descriptor for the second received message will go in 0x0604-0x0607, ..... the descriptor for the 64th message will go in 0x06FC-0x06FF and, if enabled, a Monitor Command Stack Rollover interrupt will be generated at the start of that (the 64th) message. The descriptor for the 65th message will then overwrite that for the first message, in locations 0x0600-0x0603.

That should work OK. I just suggest that during your interrupt service routine that you initialize the (A or B) Command Stack pointer to 0x0604, rather than 0x0600.

The reason is that 27 µs could be marginal for the case where the message which caused the command stack rollover is a broadcast mode code with no data words. In this case, if the intermessage gap time is 4 µs (per -1553B), there could theoretically be a gap time between the start of successive messages of about 22 µs. By initializing to 0x0604 rather than 0x0600, the message descriptor stored at 0x06000x0603 will not be overwritten.

Note, however, that the minimum intermessage gap for most bus controllers is approximately 10 µs (or more).

You may reinitialize (write to) the Command Stack Pointer location at any time. The Mini-ACE includes an arbitration circuit, to prevent "crashes" between memory accesses by the internal logic circuitry and by your host processor.

Keep in mind, the digital portion of the BU-61588 does not include any internal processor or "firmware." It's a state machine logic circuit.The Monitor Command Stack pointer is sampled to determine the starting location for the current message's 4-word descriptor, and incremented by four, and re-written during the monitor startof-message (SOM) transfer sequence.

The Mini-ACE arbitration logic prevents you from writing to memory (e.g., the Monitor Command Stack Pointer) during the monitor SOM transfer sequence.Therefore, if you write to the stack pointer before the SOM sequence, the new value will be used for the next message that comes in. However, if you write to the Command Stack Pointer after the SOM sequence for a message that has occurred, then that (current) message will store its descriptor information (Block Status Word, Time Tag, etc.) at the old (previous) location; that is, the one that was accessed during the message's SOM sequence.

If you initialize the Command Stack Pointer to 0x0604, then the 64th message, which will result in a Command Stack Rollover Interrupt (if enabled) at the start of the message, will result in the descriptor to be stored in 0x06000x0603. Therefore, if your interrupt service routine does not react fast enough, the 64th message will not overwrite a descriptor in 0x06000x0603, since there was no descriptor stored there previously.

The way that the Monitor Command Stack and Data Stack operate is that they always roll over at an address boundary of modulo the programmed stack size, regardless of the values that the pointers were initialized to.

The ACE monitor stops monitoring once an error (for example, a parity error) is detected in a message. Therefore, the monitor will not detect a subsequent response timeout condition in the same message. In fact, if there is a response to a message with an error (e.g., parity), the monitor will interpret the status word as the command word for a new message.

No. MASTER INTERRUPT will only occur for an event/condition that is enabled by means of the Interrupt Mask Register.

Here are a few things that you can look at:

1. You need to make sure that RDAD4 through RTAD0 are connected to +5V or GROUND for the correct desired RT address and that the RT address parity signal, RTADP, is connected to +5V or GND, to ensure a correct odd parity sum. That is, the number of logic "1"s for RTAD4-RTAD0 AND RTADP must be an odd number. For example, if your desired RT Address is 0, then RTADP must be connected to logic "1." If the RT address parity is incorrect, the BU-61580 RT will not recognize any messages that the BC sends to its RT address.

2. You need to provide a properly terminated 1553 bus (that is, 70 to 85 ohms at each end of the bus). An unterminated bus may result in transmission line reflections, resulting in waveform distortions. In such a case, the RT may not recognize an otherwise valid message from the bus controller.
3. Make sure that you have a clean 16 MHZ clock input to CLK_IN. Note that 16 MHZ is the default clock frequency for the BUS-61580. You may also use a 12 MHZ clock for the BU-61580, but this would require you to modify your initialization software by programming for ENHANCED mode and then programming bit 15 of Configuration Register #5 to logic "1."

In addition, you need to make sure that the clock input has a duty cycle in the range of 40% to 60%, and does not have significant undershoot, overshoot, or transition noise on the rising and falling edges. If you see any of these types of problems, they are generally layout related: either transmission line type reflections (possibly from long - more than 1 or 2 inches - "stub" traces) and/or from crosstalk from other signals on your board.

You need to make sure that the center taps of your isolation transformers are grounded on the "primary" side; that is, the side of the transformers connected to the BU-61580. If you don't ground the center taps, you might be able to receive messages from the bus controller, but the BU-61580 RT won't be able to transmit any responses.

You say that the Interrupt Mask Register is not getting corrupted. Here are some things for you to consider:

1. You should determine whether or not the BU-65170's descriptor stack pointer continues to increment. If it does, this points to an "interruptspecific" type of error. In this case, you should read the value of the messages' Block Status Words to try to gain insight into the problem. If the stack pointer is not incrementing, this points to an error receiving and processing valid messages from the 1553 bus. This could possibly be a bus controller, termination, transformer, or other electrical problem; an inadvertent change in the BU-65170's RT address; a power glitch; an inadvertent hard- ware reset (MSTCLR input pulsing low); or a software problem (e.g., inadvertently writing an incorrect value to a register).
2. What interrupt are you enabling? EOM? Others?
3. Is the BU-65170's interrupt output (INT) configured as a pulse or level type signal (bit 3 of Configuration Register #2)? Remember, if it's configured as a level, you won't get a subsequent interrupt until you first clear the INT output and Interrupt Status Register from the previous interrupt.
4. Are you using INTERRUPT STATUS AUTO CLEAR (bit 4 of Configuration Register #2)? If you are not, it is necessary to write a value of "1" to bit 2 (INTERRUPT RESET) of the Start/Reset Register in order to clear the Interrupt Status Register and the INT output (if it's programmed for "level"). If INT is programmed to provide a level type of interrupt and is not cleared following the first interrupt request, then the host will not detect subsequent interrupt requests.
5. Another thing that you might look at: try setting ENHANCED INTERRUPTS, bit 15 of Configuration Register #2 to logic "1" (note that to use this feature, it is first necessary to write a value of logic "1" to ENHANCED MODE, bit 15 of Configuration Register #3). By doing this, it is possible for bits in the Interrupt Status Register to become set, even if the respective events/conditions have been disabled from causing interrupt requests. Therefore, I would suggest to write a value of 0000h to the Interrupt Mask Register to disable all interrupts, and then periodically poll the Interrupt Status Register. In this scenario, the ISR bits (e.g., EOM) should still become set. Of course, it will then be necessary to clear the ISR by either AUTOCLEAR, or by writing a value of 0004h (INTERRUPT RESET) to the Start/Reset Register.
6. You need to make sure that the values of registers other than the Interrupt Mask Register are not changing. For example, that the upper two bits (15 and 14) of Configuration Register #1 are staying as "1" and "0" respectively (for example, a combination of "0" and "0" will cause the BU-65170 to revert to its "idle" (non-active) mode.
7. You need to verify that the BU-65170's RT address (and parity) inputs are not changing.
8. Finally, you need to ensure there isn't a hardware related problem between the BU-65170's INT output and your DSP's interrupt request input, such as logic related to interrupt requests from other hardware circuits.

By setting the MSB (bit 15) of Configuration Register 3 (ENHANCED MODE), and then writing a value of 7 (111) to the three LS bits of configuration register 4.

To illustrate by example:

• V  W  R  0003  0001 means a vector write to register 3 the value 0001.
• V  R  R  0000  0040 means a vector read (and verify) of register 0 the expected value 0040.
• V  W  M  0000  0655 means a vector write to memory location 0 the value 0655.

The problem that you are seeing has to do with the ACE's host processor responding to an interrupt request, and then reading the ISR (Interrupt Status Register). As a result, the value of the ISR is getting cleared to 0.Test register 0013h is a reading of the ACE's internal state. Register 0006 is the ISR. To prevent this problem from occurring and to enable your ACE to pass selftest, you will need to either:

1. Have the ACE's host processor disable interrupts during self-test; or
2. Make sure that the ACE's host processor does NOT read the value of the ACE's ISR during the interrupt service routine while you are in self-test.

To induce a transmitter timeout condition for the ACE/SP'ACE/Mini-ACE, set the lower three bits (TEST MODE) of Configuration Register #4 to a value of 4 (100). This configures the ACE test mode for "Failsafe timer" test mode. When you do this, the ACE will transmit until a timeout condition occurs for every transmission. That is, for every RT response, or for every BC message transmitted. The value of the failsafe timeout timer is either 668 µs for ACE or SP'ACE, or 660.5 µs for Mini-ACE or Enhanced Mini-ACE.

When the RT is in TEST MODE, the Enhanced Mini-ACE will not transmit any words on the 1553 bus.

The Mini-ACE and Enhanced MiniACE have nearly identical pinouts, with the following exceptions:

Pin 25: For Mini-ACE, this signal is "Test  Output  (RX-B)". For Enhanced Mini-ACE, this signal is INCMD_L/MCRESET_L (output).Pin 26: For Mini-ACE, this signal is "Test Output (RX-B)". For versions of the Enhanced Mini-ACE with 64K X 16 RAM (BU-61864/61865), this signal is "Vcc-RAM" (+5V). For the versions of Enhanced MiniACE with 4K X 16 RAM, this pin is UPADDREN (see below).Pin 37: For both Mini-ACE and Enhanced Mini-ACE, this signal is "Vcc-LOGIC". However, for the BU-61743, BU-61843, and BU-61864 versions of the Enhanced Mini-ACE, this voltage is +3.3V. For the BU-61745, BU-61845, and BU-61865 versions of Enhanced Mini-ACE, this voltage is +5V.Pin 65: For Mini-ACE, this signal is "Test Output   (RX-A)".  For Enhanced Mini-ACE, this signal is LOGIC GND. Pin 67: For Mini-ACE, this signal is  "Test  Output  (RX-A)".    For Enhanced Mini-ACE, this signal is LOGIC GND.

In addition, for versions of Enhanced Mini-ACE with 4K of RAM (BU61843(5) BC/RT/MT and BU-61743(5) RT), note that there are different, or potentially different pin functions on the following pins: Pin 26: UPADDREN. If this pin is logic "1," then pins 8 (A14), 66 (A15), 70 (A12), and 71 (A13) function as the upper 4 address lines, A15-A12. Note that this provides compatibility with the BU-65178 and BU-61588 MiniACE, and the BU-61688/61689 Mini-ACE Plus.

However, if UPADDREN (pin 26) is connected to logic "0", then the functions of these four pins behave more like the BU-65179 version of the Mini-ACE, as follows: Pin 8: CLK_SEL_0 Pin 66: CLK_SEL_1 CLK_SEL_1 and CLK_SEL_0 are used to designate the frequency of the CLK_IN input as follows:

Note that for all versions of Enhanced Mini-ACE, clock frequency selection may also be done via software.

Pin 70:  RT_AUTO_BOOT  If this pin is connected to logic "0," the Enhanced Mini-ACE will initialize in RT mode with the Busy bit set following power turn-on. If hardwired to logic "1," the Enhanced MiniACE will initialize in either Idle mode (if it's an RT-only part), or as in BC mode (if it's a BC/RT/MT part). Pin 71: Assuming that UPADDREN is logic "0," then this pin must be tied to Vcc-LOGIC (+5V or +3.3V).

The Enhanced Mini-ACE is available in versions for which the logic sections are powered by 3.3V. The Mini-ACE is not; its logic may only be powered by +5V. In addition, the Enhanced Mini-ACE's ENHANCED CPU ACCESS feature allows for a shorter maximum holdoff time for processor-to-ACE memory and register transfers. This time has been reduced from about 2.8 µs max (at 16 MHz) for Mini-ACE, to about 600 ns max (at 16 MHz) for Enhanced Mini-ACE.Also, for RT mode, the Enhanced MiniACE includes the following new architectural features:

1. Global circular buffer. That is, a circular buffer that may be used by all subaddresses or a subset of all subaddresses. Note that both the Mini-ACE and Enhanced Mini-ACE RTs have circular buffers that may be programmable by individual subaddresses.
2. The addition of a 50% rollover interrupt for circular buffers. Note that both the Mini-ACE and Enhanced Mini-ACE also have interrupts for (100%) circular buffer rollover.

3. An interrupt status queue. This provides a chronology of up to the last 32 interrupts, including the reason(s) for the interrupts, and pointers to the individual message descriptors.
4. Fully autonomous built-in protocol and RAM self-tests. For the MiniACE, a protocol self-test may be performed by means of the host processor writing and reading/verifying test vectors.
5. With the Enhanced Mini-ACE, there is a bit more flexibility for implementing a software programmable RT address. That is, with Mini-ACE, to do this, RTAD4-0 and RTADP must be connected to D5-D0. This means you can't select between an address from an external connector or software by means of software. With the Enhanced Mini-ACE RT, you can do this fully under software control.

The Enhanced Mini-ACE is software backfit compatible with the Mini-ACE, with the following two exceptions:

1. In the BU-61588, bit 8 of the RT BIT Word Register (and in the BIT word transmitted to the BC) is CHANNEL B/A. With the BU-61865, bit 8 is BIT TEST FAIL. It will set to a value of logic "1" if there is a failure of the Enhanced Mini-ACE's built-in protocol self-test.
2. With the Mini-ACE, to run the protocol self-test, it is necessary for the host processor to write and read/verify the test vectors. With the BU-61865 Enhanced MiniACE, all the host processor needs to do is to write a register bit; the self-test vectors are then run autonomously by the BU-61865 Enhanced Mini-ACE. When the self-test is complete, an interrupt request will be issued to the host (if enabled) and the results of the self-test will be available in a register to be read. In addition, the Enhanced Mini-ACE provides a separate additional autonomous self-test for the 4K or 64K internal RAM. Alternatively, there are self-test vectors for the Enhanced Mini-ACE that may be run from the host processor. Note however that these test vectors are different than those for the Mini-ACE.

Yes. The 3.3V Enhanced Mini-ACE is 5 volt tolerant. The absolute maximum rating for "Logic Input Voltage" is 6.0V. The Enhanced Mini-ACE's input and I/O pad cells include clamping diodes to LOGIC GROUND, but do not include clamping diodes to Vcc.

Yes. There are active pull-ups on all of the inputs and I/O, except for the clock input. More accurately, these are current sources from VCC, with the current value in the range from 50 to 350 µA. In addition, there are Schmidt triggers on all digital input signals (including I/Os), including the clock input. CLK_IN is a CMOS type input. Its V_Il is 0.2•V_CC max, its V_IH is 0.8•V_CC min, and the minimum Schmidt hysterisis window is 1 volt. The other inputs are TTL type, with V_Il = 0.7V max, V_IH = 2.1V min, and a minimum Schmidt hysterisis window of 0.4V.

There are no rollover enforcements for the Enhanced Mini-ACE's BC op code instruction list or for the Command/Status blocks.

For the Non-Enhanced BC mode (i.e., not using the autonomous BC message sequence control engine), the nominal BC intermessage gap time for the Enhanced Mini-ACE is the same as for the Mini-ACE (Plus) hybrids, approximately 9.5 µs.

However, for the Enhanced Mini-ACE's enhanced BC mode (using the autonomous message sequence control engine), the typical value for intermessage gap time is approximately 10 clock cycles longer than for the nonenhanced BC mode. This accounts for the time for the message sequence control engine to fetch op code and parameter words from the BC

Instruction List, and to execute the op code (assuming an Execute Message (XEQ) instruction). That is, an additional 1.0 µs at 10 MHz, 833 ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.Also, note that if ENHANCED CPU ACCESS, bit 14 of Configuration Register #6, is set to logic "1," the Enhanced Mini-ACE's arbitration logic will interleave host transfers in between individual SOM or EOM word transfers. In this scenario, host transfers could have the effect of lengthening the intermessage gap time.

For each host access during an SOM or EOM sequence, the intermessage gap time will be lengthened by 6 clock cycles for each host access in buffered mode, or by 7 clock cycles in transparent mode. Since there are 7 internal transfers during SOM and 5 during EOM, this could theoretically lengthen the intermessage gap (for buffered mode) by up to 72 clock cycles; i.e., up to 7.2 µs with a 10 MHz clock, 6.0 µs with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a 20 MHz clock. Note that this worst case delay would only occur in the case of a burst access by the host processor.

However, note that if you set ENHANCED CPU ACCESS to logic "0," the maximum host wait time (i.e., maximum delay from the STRBD/SELECT inputs asserted lowto-READYD output low) increases from 612 ns (for a host read) or 550 ns (for a host write) to about 2.8 µs. Therefore, the tradeoff is between increased host holdoff time (which, on average, won't occur very often) vs a potential occasional increase in the BC intermessage gap time.

The call stack pointer clears when you start the bus controller by means of the Start/Reset Register.

The general purpose queue pointer points to the next address location, modulo 64. That is, the location following the last location written by the BC.

Yes, it is safe to use these locations for control/status blocks or data blocks. In the enhanced BC mode, these locations are not "reserved."

The value of the pointer parameter in the BC instruction list (e.g., for the Execute Message instruction) must be modulo 8. That is, the three LSBs of this word must always be "000." The length of the Control/Status block should be: 8 words - for messages that are not RT-to-RT transfers and are not referenced by an XQF (Execute and Flip) instruction, or 16 words - for messages that are either RT-toRT transfers and/or are referenced by an XQF (execute and flip) instruction.

The parity bit covers the entire instruction code word, not just the op-code field. Note that the parity is odd. If the BC fetches an instruction with a parity error, an erroneous op code, and/or one of the "fixed value" bits (bits 9-5) is the wrong value, then the BC will trap out (halt), and the BC OP CODE PARITY ERROR interrupt will be issued, if enabled.

No.

The RT Global Circular Buffer is a programmable option for any subset of the 30 receive(/broadcast) and/or 30 broadcast subaddresses. The size of the global circular buffer is programmable by means of bits 11, 10, and 9 of Configuration Register #6.To enable received words for a particular receive(/broadcast) subaddress to be stored to the global circular buffer, it is necessary to program bits 15, 7, 6, and 5 of the respective subaddress control word to logic "1."

If SEPARATE BROADCAST DATA is enabled (bit 0 of Configuration Register #2 = logic "1"), then words received for non-broadcast messages may be stored in the global circular buffer.

However if SEPARATE BROADCAST DATA is enabled, then words received from broadcast messages will not be stored in the global circular buffer. In this case, the buffer scheme for words received from broadcast messages will be single-buffered, rather than global circular buffered. That is, the starting address for these words will be the value of the lookup table pointer for the respective broadcast subaddress.

The pointer to the RT circular buffer is stored in location 101 (if area A is the currently active area, per CURRENT AREA B/A, bit 13 of Configuration Register #1) or 105 (if area B is the currently active area).

In Bus Controller and Remote Terminal modes, there is a continuous on-line loopback self-test performed for each message transmitted. In the loopback self-test, the respective (CH. A or CH. B) receiver/decoder samples each word transmitted. For all words transmitted by the Enhanced Mini-ACE (or for that matter, ACE or Mini-ACE) BC or RT, the validity of the "received" version is verified. Also, there is a bit-bybit comparison check between the transmitted and received versions of the last word transmitted.

If there is a failure of the loopback selftest, the "ERROR FLAG" and "LOOP TEST FAIL" bits will be set in the message's Block Status Word. In addition, if enabled, an interrupt will be issued to the host processor. Also, in RT mode, bit 14 (for Channel B) or bit 13 (for Channel A) will be set in the RT BIT Word Register, and transmitted to the BC in response to a Transmit BIT word mode command. In addition, in RT mode, assuming that bit 2 of Configuration Register #3, RTFAIL/ RTFLAG WRAP ENABLE, is programmed to logic "1," the Terminal Flag bit will be set in the status word response to the next non-broadcast message.

As for the comprehensive protocol self-test and RAM self-test, these may be initiated by a command from the host processor at any time, by writing logic "1" to the respective bit of the Start/Reset Register. The results of these tests are then made available to the host by means of polling and/or interrupts. If the protocol self-test fails, bit 8 (BIT TEST FAIL) of the RT's BIT word and BIT Word Register will be set to logic "1." However, keep in mind that when either the protocol or RAM selftest is being performed, the Enhanced Mini-ACE will be offline; that is, not able to receive or transmit on the 1553 bus.

No. When the self-test is performed, the first part of the test stores the value of the registers temporarily into memory. When the test is complete, the register values are restored. As long as the host does not attempt a write operation before the test is complete, the final values in the registers will be the same as the initial values.

Note that the Time Tag Register will continue to increment at the same rate as prior to the start of the test (i.e., no time is lost). Also, the protocol self-test cannot be performed if the BC or Monitor is presently enabled (started), or the RT is not idle, or the memory test is currently in progress. The BC frame timer and message timers will be restored to zero, but this should not matter since these will be reinitialized when the BC is enabled.

Also, if the protocol self-test fails and assuming that RTFAIL-TO-TERMINAL FLAG AUTO-WRAP is enabled, the Terminal flag status bit will be set to logic "1" and the results of the RT's last loopback test will be lost. The command stack register, data address pointer register, and the Subaddress Control Word Register will be reset to zero. In addition, the interrupt output will be cleared; it will be re-asserted only if the BIT test complete interrupt was enabled.

While the Enhanced Mini-ACE's protocol or RAM self-test is being performed, the host may access the BIT Test Status Register (register address 1Ch). However, the host may not access any of the other registers; if it does, the self-test will be aborted.

While the test is being performed, the "PROTOCOL SELF-TEST PASSED" bit (bit 12) and "RAM BUILT-IN SELFTEST PASSED" bit (bit 5) will normally be logic "0." If you poll this register while the self-test is being performed and the "PASSED" bit for the test that's being performed returns a value of logic "1," this indicates that the bit is stuck high.

Also, after the self-test completes, you may poll the final value of the self-test ROM address register and self-test data register. These are both test registers, which are made accessible by setting 64-WORD REGISTER SPACE, bit 2 of Configuration Register #6, to a value of logic "1." Assuming that the test has run to successful completion, the expected values of these two registers are known. If one of the "PASSED" bits is logic "1," but the value of either of these registers doesn't match the expected value, this would indicate a fault in the selftest logic.

For Enhanced Mini-ACE, the protocol and RAM self-tests may be initiated by means of the Start/Reset Register (write only, register address 03). In particular, to initiate the RAM self-test, you would write a value of logic "1" to bit 9 of this register. To initiate the protocol self-test, you would write a value of logic "1" to bit 7.

The RAM test works as follows: a pattern of 0, 1, 2, 3,... is written to addresses 0, 1, 2, 3..., (data = address) and then read back and verified. After that, the inverse pattern ("data = address inverted") pattern is written, read back, and verified.

The memory test takes a total of 10 clock cycles per RAM location. That is, for each word location, it takes 5 clocks to write and read/verify the "data = address" pattern, and another 5 clocks to write and read/verify the "data = inverted address" pattern.

Therefore, for an Enhanced Mini-ACE hybrid with 4K RAM locations, it takes a total of 40,960 clock cycles to perform the memory self-test. For a clock frequency of 16 MHz, this is 2.56 ms. For a hybrid with 64K RAM locations, it takes a total of 655,360 clock cycles to run the memory self-test. For a clock frequency of 16 MHz, this is 40.96 ms

It is 5 volt powered, and intended for use in a 5 volt PCI signaling environment.

No. However, you will still be able to run essentially the same self-test for the "1553" portion of the terminal that is performed on the BU-61865 (Enhanced Mini-ACE). Note however that the stimulus/response vectors will need to be written and read/verified by the PCI host; that is, the vectors will not be included in on-chip ROM.

Yes. The BU-62865 BC/RT/MT, the 64K RAM version of the PCI Enhanced Mini-ACE, does incorporate RAM parity checking.

Total Dose:

1 Mrad Single Event Upset: 10^-7 errors per bit-day  (LET threshold of 59 Mev/mg/cm²) Single Event Latchup:

 Immune Dose Rate: 10¹⁰ rads(Si)/sec Neutron Fluence:  2•10¹³ neutrons/cm²

The ESD rating of the BU-61582's digital I/O signals is Class 1. That is, it is between 0 and 1500 volts. The MILSTD-1553 analog transceiver signals (TX/RX-A, TX/RX-A, TX/RX-B, and TX/RX-B) provide an ESD immunity level of 7,000 volts with no protection. This value may be increased by means of external circuitry, involving the use of full-wave diode bridges, and either Zener diodes or transorbs.

There are two different versions of the SP'ACE:

1. The BU-61582XX, for which the RT address is hardwired; and ...
2. The BU-61583XX, for which the RT address may be programmed by means of software control. To make the BU-61583's RT address software programmable, you would need to connect RTAD4-RTAD0 to D5-D1, and RTADP to D0.

1. Dual port RAM is significantly more expensive than conventional single-port RAM. It also uses up more real estate than using the shared RAM that's inside the SP'ACE.
2. If dual port RAM is used, the design will still need external tristate buffers for the address and data buses, to isolate the SP'ACE buses from the buses connecting to the host processor. These are necessary to enable the host to access the SP'ACE's internal registers. This entails additional real estate and cost.
3. In terms of software, there are no differences between the use of internal shared RAM and external dual port RAM.
4. The penalty in terms of bus band-width utilization for using shared, rather than dual port, RAM is very insignificant. It's a function of the level of bus traffic, but even assuming 1,000 32-word messages per second, and assuming the use of 8-bit RAM in a SP'ACE, a host bus contention situation will only occur about 2.0 to 2.5% of the time.
5. There is no difference, in terms of worst-case holdoff time between the use of dual port RAM and shared RAM. The reason is that even with external dual port RAM, there will still be a need to access the SP'ACE's registers (through the tri-state buffers). For a dual port RAM interface, the SP'ACE's host interface will need to be configured for its transparent mode. This results in a one clock cycle increase over the buffered (shared RAM) configuration in the time required to access the SP'ACE's internal registers.

In compliance with MIL-STD-1553B, the SP'ACE and all of our other 1553 products include a transmitter timeout circuit. That is, they include a circuit that operates independently from the encoder/transmitter to automatically shut down the transmitter if it attempts to transmit longer than the longest allowable transmission time of 660 µs. For the SP'ACE, the timeout value is 668 µs. If the transmitter timer (sometimes called a watchdog timer) times out, it will: (1) shut down the Manchester encoder circuit; and (2) bring the TX_INH (transmit inhibit) inputs to the CH. A or CH. B transmitter to logic "1," which shuts down the 1553 transmitter.

The recommended configuration is for us to supply you with a version of the BU-61582 SP'ACE product that is modified to bring out the TX_INH (Transmit Inhibit) signals. The SP'ACE's mode (BC, RT, Monitor, or simultaneous RT/Monitor) is selectable, by host software, by means of Configuration Register #1. Keep in mind that the SP'ACE is designed to never transmit while in Monitor mode. To provide an extra level of assurance that the SP'ACE will never transmit on the bus while in Monitor mode, I would recommend bringing out the TX_INH signals. This way, the SP'ACE monitor is prevented from transmitting by two independent methods: (1) under nonfault conditions, the SP'ACE's Monitor mode will never attempt to transmit on the 1553 bus; and (2) if there was a fault in which the monitor did attempt to transmit on the 1553 bus, the assertion of the respective TX_INH input to logic "1" by external hardware will serve to block any transmission on the 1553 bus.

Yes. The number is 5962-94A03. In addition, there is also an Altered Item Drawing (AID) from Honeywell SSEC, who is the foundry for the BU-65621 chip. Honeywell's number for the AID is 22019712.

The BU-65621 chip does not include any on-chip memory. However, we can supply a transceiverless version of the BU-61582 SP'ACE, the BU-61582X0. The BU-61582X0 hybrid includes the JRAD protocol chip that's in the BU-65621, plus 16K X 16 of internal RAM, but no transceiver.

In addition to self-test mode, the BU-65621 has five (5) normal modes of operation:

1. Bus Controller (BC)
2. Remote Terminal (RT)
3. Word Monitor
4. Selective Message Monitor
5. Simultaneous RT and Selective  Message Monitor

Honeywell's 32K X 8 RAM will work. We integrate this chip into our SP'ACE hybrid, which also includes the same "JRAD" chip that's in the BU-65621. The use of 8-bit RAM should not have any appreciable effect on throughput.

However, you should be aware that the time for your host processor to access the buffered RAM (through the BU-65621) increases by roughly a factor of two (with respect to using 16-bit wide RAM), due to the increased time to transfer data to/from the 8-bit RAM. That is, assuming a 16 MHz clock input, there will be an increase from 312 ns max to 562 ns max for an uncontended access, and an increase from about 3.0 µs to about 6.0 µs for a contended access.

If you're considering the use of the BU-65621 with the Honeywell RAM chip, note that the BU-61582X0 transceiverless SP'ACE integrates these two chips into a single 1.0 by 1.9 inch hybrid.

1. BUS-65112 uses a 12 MHZ clock, while BUS-65142 uses a 16 MHZ clock.
2. For a Transmit (RT-to-BC transfer) message: for BUS-65112, R/W is low, except that it pulses high during the transfer cycle period defined by DTREQ being high. For BUS-65142, R/W is low for the command word transfer, then goes high and stays high (it doesn't pulse).
3. The maximum DTREQ-to-DTGRT time is 1.5 µs for BUS-65112, and 2.1 µs for BUS-65142.

For BUS-65143 (+5V/-12V power), the maximum current drain is:

For +5V: 115 mA maxFor -12V: At idle (non-transmitting): 70 mA max; at 50% transmit duty cycle: 185mA max; at 100% transmit duty cycle: 305 mA max.

For the BUS-65143 power dissipation, assuming a total external dissipation of 1.4 watts {in the isolation transformer (140 mW), coupling transformer (80 mW), isolation resistors (450 mW each) and termination resistors (150 mW each)} when transmitting:

• At idle: 1.415 watts max
• At 50% duty cycle: 2.125 watts max

We recommend a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor for each of the two transceivers [VCC-CH. A(B)] pins (72 and 20), and a 0.1 µF ceramic capacitor on Vcc-LOGIC, pin 37.

"Hottest die power dissipation" refers to the active transceiver chip. That is, at any given time, the hottest die will be for the transceiver for the "active" (transmitting) bus channel; i.e., either Channel A or Channel B.

The junction-to-case thermal resistance (_JC) for Mini-ACE (Plus) is 6.8 degrees C per watt. That is, T_J = T_C + (6.8 • P_DISS), where T_J = hottest die junction temperature, T_C = hybrid case temperature, and P_DISS = hottest die dissipation.

This refers to the percentage of time that the bus controller is actually transmitting on the 1553 bus; that is, not transmitting or receiving, just transmitting. For example, if the BC sends a message with a command word + 32 data words to each of 10 RTs once per second, the duty cycle would be:

10•[(1 + 33)•(20 µs)]/1 sec = 0.66%

A. Referring to the calculation above, you can almost use the "idle" duty cycle. Whatever your actual duty cycle is, you can calculate the power usage and dissipation; it's a linear interpolation.

Yes. MIL-STD-1553 operates as a "standby redundant" bus. That is, the BC usually sends most of its messages on the "primary" bus (typically Bus A). The BC will only switch over to the secondary bus (typically Bus B) if it detects a failure on the primary bus, or if there is a failure of one (or more) RTs on the primary bus.

Clause 4.6.3.1 of MIL-STD-1553B states that "Only one data bus shall be active at a given time …" On most 1553 terminals, it is not possible to transmit on both 1553 buses simultaneously.

A. Grounding the -15V input to the BUS63125 transceiver will not damage the BUS-63125. Of course, the BUS63125 won't be able to transmit or receive in this condition.

It is advantageous for the 1553 transformers to be located as close as possible to the connector(s) where the 1553 signals leave the board.It is desirable that the connections from the transformer primaries (Mini-ACE side) center taps to your 5V RETURN (presumably the ground plane) to be as thick as possible, since these will be conducting large currents when transmitting, on the order of 500 to 600 mA. The traces from the Mini-ACE Tx/ Rx-A(B) pins to the transformer will need to conduct the same current, but at 50% duty cycle when transmitting. The traces from the transformer secondary to the 1553 stub will conduct up to about 100 to 150 mA.

The transformer improves the ESD immunity of the overall 1553 terminal. By definition, a 1553 BC or RT terminal consists of both the analog/digital circuitry (e.g., the BU-61582X2) and the isolation transformers.A MIL-STD-1553 coupling transformer is required to exhibit a minimum common-mode rejection ratio of 45 dB at 1 MHz. Since the isolation transformers that comprise part of the 1553 terminals are similarly constructed (in some cases, they're the same transformer), they will generally have the same common-mode rejection characteristics.

Assuming that the ESD disturbance is applied between one of the 1553 stub (or bus) conductors and ground (which is generally the case), the transformers' common-mode rejection will, in effect, increase the ESD immunity of the overall terminal.

For Mini-Ace and Enhanced Mini-ACE, all of the transformers that you list have the correct turns ratios of 1:2.5 direct coupled, or 1:1.79 transformer (stub) coupled. The B-3226 is a single through-hole transformer, 0.625 X 0.625, with a max height of 0.250". B-3227 is also a 0.625 X 0.625 single surface mount transformer, but with a max height of 0.275". TST-9007 is a dual transformer, 0.625 X 0.625, max height of 0.280".

Beta  Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratio. The table on page 24 provides a listing of many of these. Note that for the BU-6XXXXX4 versions of the Enhanced Mini-ACE, which includes McAir compatible transceivers, only the B-3818 or B-3819 transformers may be used. For the BU-6XXXXX3 versions, any of the transformers listed in the table may be used.

For additional information, contact BTTC at (631) 244-7393 or www.bttcbeta.com.

The mating connector is Trompeter part number PL75-47. Trompeter, a supplier of both connectors and cables for 1553, may be reached at (818) 707-2020. One type of cable that we have used is M17-176-00002.

In most cases system designers should use the 8-bit address value even if they are using a 16-bit processor and the DD-42900 is connected for 16-bit mode. In some rare cases, 16-bit processors which don’t use byte addressing can be connected to the DD-42900 by grounding the A0 input on the DD-42900 and connecting A0 on the processor to A1 on the DD-42900. It is only for these cases where the address bus between the host and the DD-42900 is shifted by one bit that the address (relative to the processor) is listed as the 16-bit address in the data sheet. Connecting the processor this way helps save memory mapped address space for the system designer. (Note: DD-42900 Users anuals published after 1997, 1999, 2000 Data Device Corporation October 1997 will no longer contain references to “16-bit addresses.”)

The INT/MOT input signal should be left unconnected (or tied to a logic 1) for an Intel mode interface and  rounded for a Motorola mode interface. The INT/MOT signal merely provides some front end signal gating for the READ and WRITE signals generated internally to the DD-42900. When in Intel mode, these signals are developed directly from the READ and WRITE input pins. When in Motorola mode, these signals are developed from the  D/WR and DS (Data Strobe) input signals. The INT/MOT input does not have any effect on the byte or word  dering of multi-byte and multi-word transfers. The address polarity inputs (POL SEL A0 and POL SEL A1) are used to control the byte and word transfer order (big endian and little endian modes).

Each of the POL SEL input signals should either be left unconnected (these signals are pulled up internally) or grounded. The POL SEL signals only effect 16- and 32-bit transfers to and from the DD-42900. They do not affect the addressing of 8-bit control or status registers. The POL SEL A0 is only used when the DD-42900 is operated in 8-bit mode. When the DD-42900 is operated in 16-bit mode, the POL SEL A0 must be connected to ground. The  POL SEL A0 controls the order in which the high and low order bytes of a (16-bit) word are written to and read from the DD-42900. When POL SEL A0 is a logic one then the high order byte of a word is written in address X and the low order byte is written in address X+1. This is the scheme typically employed by Motorola processors. When POL SEL A0 is a logic zero then the low order byte of a word is written in address X and the high order byte is written in address X+1. This is the scheme typically employed by Intel processors. The POL SEL A1 controls the order in which the high and low order words of a 32-bit word are written to and read from the DD-42900. When POL SEL
A1 is a logic one then the high order word of a 32-bit word is written in address X and the low order word is written in address X+2. When POL SEL A1 is a logic zero then the low order word of a 32-bit word is written in address X and the high order word is written in address X+2.

The Data Match table “skips” every other word to maintain a constant offset for each corresponding Data RAM location. Each Data RAM location is a full 32-bits wide. The address of the Data RAM location is always 200 (hexadecimal) less than its corresponding Data Match Table entry. Because of this mapping, when writing to address 200h, the same 16-bit data will appear at both 200h and 202h. The effect of this mapping is that between the addresses of 200h to 3FFh the A1 bit of the address bus, which is internal to the DD-42900, is not used.

The DD-42900 can enter a Master Reset State either via hardware, by momentarily asserting the MASTER RESET input signal or via software, by writing a logic 1 into the LSB of the Master Control Register. Once in a Master Reset State, the DD-42900 is automatically “off-line” and will not respond to any software or hardware functions until taken out of the master reset state by writing a logic zero to the LSB of the Master Control Register. It is specially important to take the DD-42900 out of the Master Reset State before attempting to read any data from the DD-42900 on systems that have either the DTACK or READY signals connected to the host processor. A good way to tell if the DD-42900 is out of reset mode is to look at the 1MHz ARINC CLK output. If this clock is running then the DD-42900 is not in the reset state.

Yes. The interrupt outputs on the DD-42900 provide additional capability to systems which have interrupts available. Connecting the interrupt outputs to the host processor is optional. The interrupt features can be used to help quickly detect new receive data; FIFO full or empty conditions or an error condition. All of these conditions can be detected without the use of interrupts by polling various registers and memory locations inside the DD- 42900. Even if the IRQ output signals are not connected to the host processor, the IRQ registers can still be useful to the system programmer; the DD- 42900 can be set up so the IRQ serves as a single location for the host to poll to determine if any significant events have occurred instead of polling several different registers. This can speed up polling routines. The IRQ outputs may also be useful when made available as a test point for system debugging. An IRQ output set for pulse mode may be used to detect error conditions or to trigger a logic analyzer or oscilloscope to a particular ARINC-429 message or group of messages. 

The short answer is that there is absolutely no difference in the actual timing of the device. The DD-42900 Users Manual provides two sets of timing information, synchronous and asynchronous. These two sets of timing information describe the timing of the DD-42900 in two different ways. The synchronous timing information describes the read and write cycles relative to the DD-42900 clock. If the processor is running from the same clock as the DD-42900, or a derivative of this clock, then these timing diagrams and tables will provide the system designer with the shortest read and write cycle possibilities.

The asynchronous timing information describes the read and write cycles of the DD- 42900 without any reference to the DD-42900 clock. If your processor is using a different clock than the DD- 42900 the asynchronous timing diagrams and tables provide the timing information needed to guarantee proper operation. Because the DD-42900 is a synchronous device, the read and write cycle times on the asynchronous timing diagrams may appear slightly longer. This is to ensure that set up and hold times are met for various input signals relative to the DD-42900 clock. The system designer is free to choose which set of timing information is most useful for their application.

Yes. It is important to note that write cycles do not require the DTACK or READY handshake signals at all because both the data and address information from the processor are latched internally to the DD-42900 upon the rising edge of the write signal, even if the DD-42900 is not immediately ready to write the data to its final destination. It is also important to note that DTACK and READY are only required on read cycles from Data Store RAM or Data Match RAM. These are denoted as Type 3 Reads on the DD-42900 data sheet and may take several clock cycles longer than a Type 1 or 2 read. This is because the RAM is shared between the host processor and the internal DD-42900 processors. There are two ways that the DD- 42900 can operate properly without the DTACK or READY handshake signals. First, if your processor read cycle is long enough to guarantee that a DTACK would occur before the data from the DD-42900 is sampled for a Type 3 Read Cycle then use of the DTACK or READY handshake is not necessary. Check the timing data in the DD-42900 data sheet for the maximum time to valid data for a Type 3 Read Cycle. Second, the DD-42900 can be used in ZERO WAIT mode which provides the system designer with a method to avoid using DTACK or READY signals to read data from the DD-42900. To use the zero wait mode the ZERO WAIT pin on the DD-42900 must be grounded. In this mode, the software designer must program a dummy read at the address where a read is to be performed. The data obtained from this dummy read should be discarded by the software. The DD-42900 internally fetches the data after the dummy read cycle to an internal data latch. The internal data latch will hold the entire 16- or 32-bit value requested. Subsequent reads to the same address or addresses within the same 16- or 32-bit word can be read as Type 2 reads which require a minimum number of clock cycles for proper access. See the DD-42900 data sheet for the timing requirements of Type 1, Type 2 and Type 3 read cycles. 

Most ARINC-429 avionic subsystems only require the data from a few addresses. It is in these cases that the DD-42900 works hardest for the system designer by providing the functionality needed by sorting and storing only the data that the system needs and ignoring all the rest. If, however, a system requires all or most of the data to be received, this can be accomplished by using the wild card features in the Data Match Table. The Data Match Table architecture provides a lot of functionality that may not be obvious to the system designer. For example, if a system designer wished to receive data from most addresses, but not all, the designer can program those addresses NOT desired first in the Data Match Table and then place a wild card in the Data Match Table. Since the DD-42900 scans the Data Match Table from the beginning for each word received, the data not desired will be stored in locations which can be ignored by the system. The location corresponding to the wild card location, or Receive FIFO, will contain all data received except those not desired.

The ARINC CLK 0 and ARINC CLK 1 are normally tied to the ARINC clock output (1 MHz) to provide precisely 100k bps or 12.5k bps data rates. When an application requires the use of a different transmit and receive frequency, the ARINC CLK inputs can be tied to a clock which is less than 1 MHz or as high as 1.16MHz. The speed of these clocks will determine the ARINC-429 data transmit and ARINC-429 receive rates for their respective transmit and receive channels. ARINC CLK 0 affects the transmit rate on Tx0 and receive rates on channels Rx0 and Rx1. ARINC CLK 1 affects the transmit rate on Tx1 and receive rates on channels Rx2 and Rx3. The Transmit/Receive frequency is 1/10th the clock frequency when the ARINC-429 channel is programmed for high-speed and is 1/80th the clock frequency when the ARINC-429 channel is programmed for low-speed. For example, if the input clock were 800 KHz, then the transmit rate for highspeed would be 80k bps and 10k bps in low-speed. The transmit and receive rate control bits are programmed in the ARINC Control Register 1.